1. Field of the Invention
The present invention relates to integrated circuit semiconductor device technology and, more particularly, to an apparatus and method for achieving mechanical and thermal isolation of portions of integrated monolithic circuits.
2. Description of the Related Art
Semiconductor package stress and thermal gradients tend to degrade the precision and accuracy of analog integrated circuits. For example, an operational amplifier's input and output tolerances tend to shift during package assembly due to the stress imposed on the semiconductor die. This phenomenon is known as "assembly shift". Usually, however, only a small portion of the semiconductor die has stress/thermal sensitive components. Such sensitive components include matched pairs in input stages, band-gap references, and R-2R ladders. The sensitive components can usually be collected together in one area of the die.
A few sources of package stress include the scribing and separation of the die, bonding of the die to a lead frame, stress caused by the molding compound, and lead frame twist. The stress caused by the molding compound results from the curing of the compound, internal particles in the compound pressing on the die, and aging of the compound. Lead frame twist is caused by tab cutoff and the mounting and soldering of the PC board.
A few sources of thermal gradients in the sensitive component areas of the semiconductor die include heat conduction from the rest of the die, power sources and heat sinks on the die, and external heat sources. Heat generated by external heat sources is transferred to the die through the molding compound and through leads.
Previous methods of reducing package-induced stress effects have focused on reducing the stress that is transferred to the entire semiconductor die by the package leadframe, die bonding material, and molding compound. These methods, however, have not been fully effective, partly because they attempt to protect the entire die when only a small portion of the die actually requires stress/thermal protection.
The semiconductor device microstructure disclosed in U.S. Pat. No. 4,696,188 to Higashi attempts to provide an environment of substantial physical and thermal isolation between an electric element and a semiconductor body. However, the Higashi device suffers from the disadvantage that the electric element is not contained in a totally sealed environment.
Thus, there is a need for an apparatus and method for reducing the stress and thermal gradients transferred to the sensitive components of a semiconductor die that overcomes the disadvantages of the methods described above.